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Parallel RISC Architecture . A Functional Approach Based on Backus ’ s FP language
| Content Provider | Semantic Scholar |
|---|---|
| Author | Malita, Mihaela Stefan, Gheorghe |
| Copyright Year | 2011 |
| Abstract | The main consequence of building ad hoc structured hardware for parallel computation is the huge difficulty we have to program it. The paper discusses a new framework introducing the concept of parallel RISC engine, as a simple and efficient solution for executing FP like languages proposed by John Backus [2] as an alternative to the von Neumann style of performing computation. A first version for the hardware solution is already implemented in silicon [12]. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://users.dcae.pub.ro/~gstefan/2ndLevel/technicalTexts/2011_PDPTA.pdf |
| Alternate Webpage(s) | http://www.arh.pub.ro/gstefan/2011_PDPTA.pdf |
| Alternate Webpage(s) | http://worldcomp-proceedings.com/proc/p2011/PDP4300.pdf |
| Alternate Webpage(s) | http://world-comp.org/p2011/PDP4300.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |