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Improvement of Thickness Uniformity of Silicon and Soi Wafer by Numerically Controlled Local Wet Etching
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yamamura, Kazuya Mitani, Takuro Zettsu, Nobuyuki |
| Copyright Year | 2008 |
| Abstract | INTRODUCTION Silicon on insulator (SOI) wafers are promising semiconductor material. The applying of the SOI substrate realizes high speed LSIs and low power consumption electronic devices by the reduction of parasitic junction capacitance . Furthermore, the occurrence probability of a soft error caused by exposure to radiation and neutrons can be reduced because the device layer is completely insulated from the substrate by the buried oxide (BOX) layer. In the next generation’s specifications, required thickness and its uniformity of the SOI layer to fabricate the fully depleted metal oxide semiconductor transistor are 13-15 nm and ±5 %, respectively . |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.aspe.net/publications/Annual_2008/POSTERS/11NOVEQ/2675.PDF |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
