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Fpga Implementation of Image Encryption and Decryption Using Aes Algorithm Along With Key Encryption
| Content Provider | Semantic Scholar |
|---|---|
| Author | Rajoriya, Parul Mohota, Nilesh A. |
| Copyright Year | 2017 |
| Abstract | The importance of cryptography applied to security in electronic data transactions has acquired an essential relevance during the last few years. A proposed FPGA-based implementation of the Advanced Encryption Standard(AES) algorithm along with key encryption for images is presented in this paper. An efficient image encryption scheme based on FPGA using AES algorithm integrated with RC4 encryption standard is proposed. The use of RC4 algorithm imparts additional level of security to the encryption. The design converts the original image into its hex values using Matlab and then give it as input to the proposed AES. The key input given to AES is further encrypted using RC4 encryption algorithm. The encrypted image is decrypted using AES decryption algorithm. The encrypted key is decrypted using RC4 decryption algorithm so as to give it as input to the AES decryption algorithm. The encrypted and decrypted image can be analysed in Matlab. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Keywords— AES algorithm, RC4 algorithm, image encryption, key encryption, image decryption, key decryption |
| Starting Page | 40 |
| Ending Page | 50 |
| Page Count | 11 |
| File Format | PDF HTM / HTML |
| Volume Number | 12 |
| Alternate Webpage(s) | http://www.iosrjournals.org/iosr-jece/papers/Vol.%2012%20Issue%203/Version-2/G1203024050.pdf |
| Alternate Webpage(s) | http://techchronicle.in/wp-content/uploads/2017/03/18_Parul_Rajoriya_v2_i2.pdf |
| Alternate Webpage(s) | https://doi.org/10.9790/2834-1203024050 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
