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SOS CMOS 16 bit Parallel Multiplier
| Content Provider | Semantic Scholar |
|---|---|
| Author | Fukuma, Masao Ohno, Yasuo Okuto, Yuji |
| Copyright Year | 1981 |
| Abstract | As rnultiplication is essential in digital signal processing, nany reports have been published on multiplier LSIrI'2). In this paper, a high perfornance 16 bit parallel nultiplier is presented. It features S0S CMOS, which is suitable for logic LSI applications. The nultiplier configuration is shown in Fig.1, i.€., Ful1 adder (f/A)+NOR cellular array. Device parameters and design rule outline are listed in Table 1. Although Si islands were forned by conventional anisotropic-etching method, gateoxide break-down voltage is kept sufficiently high. Specially developed 1-D process-aevicJ) and. 2-D device4) simulators were utilized for fine pattern SOS M0SFET design, i.e., short-channel effect and back-channel leakage current suppressions. In circuit and mask pattern design, special design methods, due to S0S CM0S, can be used. rtSum'r and rrcarry" citcuits were designed separately, because of a high speed operation requirement (Fig.2). However, occupied area increase is relatively small. The n* or p+ doped epitaxial Si layer is widely used as a signal line. This leads to higher packing density and less pattern design tine without any additional parasitic capacitance. Parasitit capacitance, except at a line cross over point, can be ignored in circuit optimization process. F/A+NOR cel1 size is 230x190;.rm and chip size is 5.02x4.87mm. In order to evaluate multiplier performance accuratly, F/A ring oscillator was fabricated on the same wafer as the rnultiplier. Functional tests were perforned by randomly selected input patterns. Maxinum multiplying tine, ?n.U , is observed when the signal propagates through the bold line arrow path, as indicated in Fig.L. t*J and average power, P^r, vs. supply voltage, Vee , relationships were obtained, as shown in Fig.3. This nultiplying time depends on F/A propagation delay,G^. Conparison between measured (F/A ring oscillator) and calculated (circuit sinulation) Gl" are shown in Fig.4. They are almost the same in wide Voo range. Using the simulated Q;, G*l c"n be estimated as Gd =GA x3l+ft1ox+?ro . Here, ?rroe and Tvo correspond to NOR gate and I/0 buffer delays, respectivly. Predicted fr,""[ shows good agreement with the experimental data, as shown in Fig.5. Performance comparison with other nultipliers is shown in Fig.6. S0S CMOS has an advantage over other devices. In conclusion, the SOS CMOS 16 bit paral1el multiplier operates with G*l = 65nsec and Pqy =250nW at \,(o=5y. SOS CMOS can realize expected high perfornance LSIs with good designability and high producibility. |
| File Format | PDF HTM / HTML |
| DOI | 10.7567/SSDM.1981.A-2-2 |
| Alternate Webpage(s) | https://confit.atlas.jp/guide/event-img/ssdm1981/A-2-2/public/pdf_archive?type=in |
| Alternate Webpage(s) | https://doi.org/10.7567/SSDM.1981.A-2-2 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
