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Improving the Protection of Fpga Based Sequential Ip Core Designs Using Hierarchical Watermarking Technique
| Content Provider | Semantic Scholar |
|---|---|
| Author | Meenakumari, M. Athisha, G. |
| Copyright Year | 2014 |
| Abstract | In recent years, Intellectual Property (IP) cores in Very Large Scale Integration (VLSI) have become an active research area as it provides a new-fangled revolution in the Electronic Design Automation industry. An IP core is a previously designed and demonstrated component that can be integrated into design. Owing to the development of IP cores, time consumption becomes less and the product can be arrived in specified time. Designer of VLSI IP cores needs assurance that the design will not be illegally redistributed by consumers. IP core vendors are facing a major challenge to avoid revenue loss due to IP piracy. Watermarking is a well-known technique to protect an unauthorized use of IP core. Finite State Machine (FSM) is one of the representations of sequential digital designs. In this paper, a new dynamic hierarchical watermarking scheme is proposed. The watermark is embedded in the state transitions of FSM at the behavioural level. A watermark is embedded into FSM by hierarchically splitting original FSM into smaller FSMs. Experimental results on benchmark circuits shows that this hierarchical watermarking approach is an efficient method for protecting sequential IP cores. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.jatit.org/volumes/Vol63No3/17Vol63No3.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
