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New directions for fpga ip core watermarking and identification.
| Content Provider | CiteSeerX |
|---|---|
| Author | Ziener, Daniel Teich, Jürgen |
| Abstract | Abstract. In this paper, we present an overview of new watermarking and identification techniques for FPGA IP cores. Unlike most existing watermarking techniques, the focus of our techniques lies on ease of verification, even if the protected cores are embedded into a product. Moreover, we have concentrated on higher abstraction levels for embedding the watermark, particularly at the logic level, where IP cores are distributed as netlist cores. With the presented watermarking methods, it is possible to watermark IP cores at the logic level and identify them with a high likelihood and in a reproducible way in a purchased product from a company that is suspected to have committed IP fraud. The investigated techniques establish the authorship by verification of either an FPGA bitfile or the power consumption of a given FPGA. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Fpga Ip Core Watermarking New Direction Logic Level Ip Core Fpga Ip Core High Likelihood Abstraction Level Reproducible Way Power Consumption Identification Technique New Watermarking Netlist Core Protected Core Presented Watermarking Method Purchased Product Fpga Bitfile Investigated Technique Ip Fraud |
| Content Type | Text |
| Resource Type | Article |
