NDLI: 24 GHz stacked power amplifier with optimum inter-stage matching using 0.13 μm CMOS process

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24 GHz stacked power amplifier with optimum inter-stage matching using 0.13 μm CMOS process

Content Provider	Semantic Scholar
Author	Chang, Jiyoung Kim, Kihyun Lee, Sungho Nam, Sangwook
Copyright Year	2011
Abstract	A single-stage 24 GHz triple stacked power amplifier using 0.13 μm CMOS process is demonstrated. To Compare with parallel current combining method, series voltage combining method using a stacked amplifier architecture can realize a large output voltage swing from the top transistor without exceeding the transistor breakdown voltage limitations. However, at high frequencies, parasitic capacitances at the drain of each transistor become significant and it cause the phase difference between output current and voltage swing which degrades the performance of the power amplifier (PA). To solve this problem, the optimum inter-stage matching technique using inductors is introduced. With proposed optimum inter-stage matching method, the power amplifier performs a gain of 12.2 dB and saturated output power of 17.5 dBm with power added efficiency (PAE) of 20.5%. The 3dB output bandwidth is from 20.7–26.8 GHz.
Starting Page	1
Ending Page	3
Page Count	3
File Format	PDF HTM / HTML
Alternate Webpage(s)	http://ael.snu.ac.kr/paper_file/APSAR_2011_Chang.pdf?origin=publication_detail
Alternate Webpage(s)	http://ael.snu.ac.kr/paper_file/APSAR_2011_Chang.pdf
Journal	2011 3rd International Asia-Pacific Conference on Synthetic Aperture Radar (APSAR)
Language	English
Access Restriction	Open
Content Type	Text
Resource Type	Article

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