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An Ultra-Low-Power 24 GHz Low-Noise Amplifier Using 0.13 CMOS Technology
| Content Provider | CiteSeerX |
|---|---|
| Author | Cho, Wei-Han Hsu, Shawn S. H. |
| Abstract | Abstract—This study presents an ultra-low-power 24 GHz low-noise amplifier (LNA) using 0.13 CMOS technology. We pro-pose of using the minimum noise measure () as the guideline to determine the optimal bias and geometry of the transistors in the circuit. The power-constrained simultaneous noise and input matching (PCSNIM) technique is also employed for this design. With the proposed design approach, the LNA achieves a peak gain of 9.2 dB and a minimum NF of 3.7 dB under a supply voltage of 1 V. The associated power consumption is only 2.78 mW. Index Terms—CMOS, k-band, low-noise amplifier (LNA), low power. I. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Cmos Technology Ghz Low-noise Amplifier Using Minimum Nf Low Power Input Matching Associated Power Consumption Power-constrained Simultaneous Noise Index Term Cmos Optimal Bias Minimum Noise Measure Ghz Low-noise Amplifier Supply Voltage Design Approach Peak Gain Low-noise Amplifier |
| Content Type | Text |
