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Exact Algorithm for Modifying Bu er Trees Using Bu erDuplication in a Delay Optimization
| Content Provider | Semantic Scholar |
|---|---|
| Author | Srivastava, P. Chen, Chunhong Department, Majid Sarrafzadeh |
| Copyright Year | 2001 |
| Abstract | Delay reduction has become an issue of primary importance in the VLSI industry. Various strategies of delay improvement have been suggested. Buuer Insertion is one such widely used technique. The result obtained by buuer insertion relies heavily on the buuer tree topology on which buuer insertion is done. Avenues for modiica-tion of an existing buuer tree have not been explored. In this paper we propose an exact algorithm for modifying a buuer tree through buuer duplication. We provide the proof of optimality. Through our experimental result we illustrate the strength of our algorithm. Quantitatively our algorithm gave improvements as high as 17:6% improvement in delay with a reduction of 16:6% in area over the best result obtained without duplication on a buuer tree with un-sized buuers. Similarly on a sized buuer tree (buuer sizing done to improve delay) we got improvements as high as 20:2% in delay with a reduction in area of 6:67%. Hence we show that for very similar or lesser area penalty we can obtain better delay over pure buuer insertion. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.cs.ucla.edu/~chchen/public/ankur_dac01.ps |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
