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Wiresizing with Bu er Placement and Sizing for Power-Delay Tradeo s
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shah, Jatan C. Sapatnekar, Sachin S. |
| Copyright Year | 1996 |
| Abstract | With the increasing in uence of the resistive e ects of interconnects on the performance of VLSI systems, a greater stress is being laid on careful interconnect design. One prominent technique is the approach of sizing wires for long interconnects to achieve the desired speed and power characteristics [1{4]. It has also been suggested that one may appropriately insert repeaters [5] for signi cant delay reductions. This paper uni es these approaches to optimizing an interconnect by placing a prespeci ed number of bu ers (drivers and repeaters) using a dynamic programming procedure and then performing simultaneous wire and bu er sizing using a sensitivity-based heuristic. Experimental results are presented to prove the utility and performance of the approach. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ece.umn.edu/users/sachin/conf/vlsi96.pdf |
| Alternate Webpage(s) | http://www.ece.umn.edu/~sachin/conf/vlsi96.pdf |
| Alternate Webpage(s) | http://www.ee.umn.edu/users/sachin/conf/vlsi96.pdf |
| Alternate Webpage(s) | http://www.ee.umn.edu/users/sachin/PUBS/vlsi96.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
