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Design of Efficient 4×4 Quaternary Vedic Multiplier Using Current-Mode Multi-Valued Logic
| Content Provider | Semantic Scholar |
|---|---|
| Author | Shende, Ashish S. Gaikwad, Mahendra A. Dandekar, Deepak R. |
| Copyright Year | 2014 |
| Abstract | Vedic multiplier is based on ancient Indian Vedic mathematics that offers simpler and hierarchical structure. Multi-valued logic results in the effective utilization of interconnections, which reduces the chip size and delay. This paper proposes a new design of 4×4 Vedic multiplier using quaternary current-mode multi-valued logic, equivalent to iplier has very low transistor-count and consumes very low power as compared to other multiplier designs. Since the performance of a digital signal processor depends mainly on the multipliers used, the proposed approach can greatly enhance the performance of a digital signal processing system. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://searchdl.org/public/journals/2014/IJRTET/10/2/24.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
