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An Efficient Design of Vedic Multiplier Using Pass Transistor Logic
| Content Provider | Semantic Scholar |
|---|---|
| Author | Divya, Emjala |
| Copyright Year | 2016 |
| Abstract | Pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages. Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for high speed computing. This paper proposes 4-bit and 8-bit multiplier architectures based on Urdhva Tiryakbhyam sutra. These low power designs are realized in 45 nm CMOS Process technology using Mirowind and DSCH3.5 tool. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://www.ijmetmr.com/oljune2016/EmjalaDivya-YDavidSolomonRaju-73.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
