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Novel Quantum Cost Efficient D Flip-Flop andD Latch
| Content Provider | Semantic Scholar |
|---|---|
| Author | Prem Kumar. G. |
| Copyright Year | 2014 |
| Abstract | a fault tolerant reversible logic has gained Importance as they consume low power and less heat Dissipation. The benefits of logical reversibility can be gained only after employing physical reversibility. Every future Technology will have to use reversible gates in order to reduce Power. In this paper, a new fault tolerant reversible 4*4 RR-gate which satisfies the reversible and parity preserving properties. The D-latch and D-flip flop is designed using proposed 4*4 RR-gate fault tolerant reversible gate. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. The proposed design is more efficient than the existing designs In terms of power, delay and power delay product. |
| Starting Page | 300 |
| Ending Page | 306 |
| Page Count | 7 |
| File Format | PDF HTM / HTML |
| Volume Number | 2 |
| Alternate Webpage(s) | http://www.scientistlink.com/ijcsec/2014/1V2I3300306.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
