Relaxed Simulated Tempering for VLSI Floorplan Designs (1999)

Content Provider	CiteSeerX
Author	Cong, Jason Liu, Jun S. Wong, Wing Hung Xu, Dongmin Liang, Faming Tianming, Jason Cong
Abstract	In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is designed to overcome the drawback in simulated annealing when the problem has a rough energy landscape with many local minima separated by high energy barriers. In this paper, we have successfully applied a version of relaxed simulated tempering to slicing floorplan design with consideration of both area and wirelength optimization. Good experimental results were obtained.
File Format	PDF
Journal	Proc. Asia and South Pacific Design Automation Conf
Publisher Date	1999-01-01
Access Restriction	Open
Subject Keyword	Vlsi Floorplan Design Good Experimental Result New Monte Carlo Many Local Minimum Simulated Annealing Technique Many Scientific Problem Vlsi Design Many Np-hard Optimization Problem High Energy Barrier Floorplan Design Wirelength Optimization Relaxed Simulated Tempering Rough Energy Landscape
Content Type	Text