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SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics
| Content Provider | Semantic Scholar |
|---|---|
| Author | Yan-Rong, Cao Xiao-Hua, Ma Shi-Gang, Hu |
| Copyright Year | 2008 |
| Abstract | Negative bias temperature instability (NBTI) and stress-induced leakage current (SILC) both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts: the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress. |
| Starting Page | 1427 |
| Ending Page | 1430 |
| Page Count | 4 |
| File Format | PDF HTM / HTML |
| DOI | 10.1088/0256-307X/25/4/071 |
| Volume Number | 25 |
| Alternate Webpage(s) | https://www.xidian.edu.cn/hyjsktz/docs/20110402111829680965.pdf |
| Alternate Webpage(s) | https://doi.org/10.1088/0256-307X%2F25%2F4%2F071 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
