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A Comparison of Traditional and VLIW DSP Architectures for Compiled DSP Applications
| Content Provider | Semantic Scholar |
|---|---|
| Author | Saghir, Mazen A. R. Chow, Paul Lee, Corinna G. |
| Copyright Year | 2003 |
| Abstract | The high performance and low cost of traditional programmable DSPs are achieved through the use of architectural features optimized for the computationally-intensive operations in the inner loops of common DSP algorithms. Tightly-encoded instruction sets reduce instruction storage and bandwidth requirements, but limits the use of on-chip registers or accumulators. The specialized architectural features and tightly-encoded instruction sets make DSPs difficult targets for high-level language (HLL) compilers. Since commercial DSP compilers are often less sophisticated than optimizing compilers targeting general-purpose processors, DSPs must still be programmed in assembly language to achieve the most efficient and compact code. With the proliferation of DSPs as programmable cores in embedded systems-on-a-chip, the growing complexity of DSP applications, and the continued reduction in time-tomarket cycles, more compiler-friendly DSP architectures and better DSP compiler technology are needed. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | https://staff.aub.edu.lb/~mazen/publications/workshops/wsp_1998_001/CASES98.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
