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Maximum Power Estimation for Sequential CircuitsUsing a Test Generation Based Technique
| Content Provider | Semantic Scholar |
|---|---|
| Author | Roy, Kaushik Electrical, Tan-Li Chou |
| Copyright Year | 1996 |
| Abstract | With the high demand for reliability and performance, accurate estimation of maximum instantaneous power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and optimizing the power and ground routing. However, the problem of determining the input patterns to induce maximum current, and hence, the maximum power, is NP-complete. In this paper, we present an Automatic Test Generation (ATG) based technique to eeciently estimate maximum power dissi-pation in sequential circuits. The technique can generate tight lower bounds of maximum instantaneous power within very short CPU time compared to random simulation based techniques. In addition, we also generate the measure of the quality or eeec-tiveness of our approach from a statistical point of view. Experiments were performed on ISCAS-89 sequential circuit benchmarks. Results show that the ATG-based estimation is superior to traditional simulation-based technique in both speed and performance. For large circuits, the ATG approach is on an average 29% better and 37099% faster than simulation based technique. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://dynamo.ecn.purdue.edu/~vlsi/papers/Chuanyu/cicc.ps |
| Language | English |
| Access Restriction | Open |
| Subject Keyword | Benchmark (computing) CMOS CPU (central processing unit of computer system) Central processing unit Experiment Maximum power transfer theorem NP-completeness Routing Sequential logic Simulation |
| Content Type | Text |
| Resource Type | Article |
