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Deterministic Clock Gating to Eliminate Wasteful Activity in Out-of-Order Superscalar Processors due to Wrong-path Instructions
| Content Provider | Semantic Scholar |
|---|---|
| Author | Mohyuddin, Nasir Patel, Kimish Pedram, Massoud |
| Copyright Year | 2009 |
| Abstract | 1 This research was sponsored in part by a grant from the National Science Foundation. Abstract In this paper we present deterministic clock gating schemes for various micro architectural blocks of a modern out-of-order superscalar processor. We propose to make use of 1) idle stages of the pipelined function units (FUs) and 2) wrong-path instruction execution during branch mis-prediction, in order to clock gate various stages of FUs. The baseline Pipelined Functional unit Clock Gating (PFCG), presented for evaluation purpose only, disables the clock on idle stages and thus results in 13.93% chip-wide energy saving. Wrong-path instruction Clock Gating (WPCG) detects wrong-path instructions in the event of branch misprediction and prevents them from being issued to the FUs, and subsequently, disables the clock of these FUs along with reducing the stress on register file and cache. Simulations demonstrate that more than 92% of all wrong-path instructions can be detected and stopped from being executed. The WPCG architecture results in 16.26% chip-wide energy savings which is 2.33% more than that of the baseline PFCG scheme. |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://sportlab.usc.edu/~kimish/Publication1_files/Clock%20Gating%20Paper%20ICCD09%20Camera%20Ready%207%20Pages%20.vSubmitted.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
