Loading...
Please wait, while we are loading the content...
Similar Documents
Low-temperature characteristics of well-type guard rings in epitaxial CMOS
| Content Provider | Semantic Scholar |
|---|---|
| Author | Huang, Chih-Yao Chen, Ming-Jer Jeng, Jeng-Kuo Wu, Ching-Yuan |
| Copyright Year | 1996 |
| Abstract | Characterization and simulation of minority-carrier well-type guard rings in epitaxial substrate at 77 K were performed and compared with those at RT. The escape probability in a narrow guard-ring structure under the same amount of minority carrier injection increases by about one order of magnitude when temperature decreases to 77 K. This degradation in the guard-ring efficiency can be attributed to the enhanced drift mechanism in the conductivity-modulated layer between the well bottom junction and the epitaxial high/low junction at 77 K. In contrast, this mechanism enhances the width dependence of the escape probability at 77 K. The higher minority-carrier recombination velocity of the epitaxial high-low junction contributes to the stronger width dependence secondarily. When the epitaxial layer thickness becomes thinner, the simulation also demonstrates a stronger width dependence of the escape current as well as a reduction in its magnitude. A lightly-doped epitaxial layer on a heavily-doped substrate exhibits even more importance in the guard ring efficiency for low temperature operation, and its thickness should be kept as thin as possible. |
| Starting Page | 2249 |
| Ending Page | 2260 |
| Page Count | 12 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/16.544418 |
| Volume Number | 43 |
| Alternate Webpage(s) | https://ir.nctu.edu.tw/bitstream/11536/899/1/A1996VU87900027.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/16.544418 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
