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Thermal Management of Many-Core Processors using Power Multiplexing
| Content Provider | Semantic Scholar |
|---|---|
| Author | Woodruff, George W. |
| Copyright Year | 2013 |
| Abstract | power). is brings new opportunities for the dynamic thermal management (DTM) techniques, and their role to address the challenges of power dissipation in many-core processors becomes very important. Many DTM techniques have been explored such as clock gating, dynamic voltage and frequency scaling, and thread migration for single and multi-core processors [6-9]. All these reactive methods can have power and performance overhead apart from the hardware and software implications. Power multiplexing which is a proactive method can be utilized as a supplementary approach to the reactive methods for eff ective thermal management of many-core processors [10, 11]. Power multiplexing technique involves redistribution (or migration) of the workload of the cores in the chip at regular time intervals to control the thermal profi le on the chip. is approach is diff erent from the reactive DTM techniques which wait for the temperature to increase beyond a certain threshold value. e idea is to improve the thermal profi le by using idle or underutilized cores effi ciently. e guiding rule which governs the redistribution of workload is called migration policy. e time interval at which this migration takes place is referred to as timeslice. A smaller timeslice corresponds to faster multiplexing. e value for the timeslice is typically chosen such that it is smaller than the characteristics thermal time constant (τ) of the system. In the present case, this time constant cooling methods begin to reach their fl ow and acoustic limits for very high power density (~1.5 W/mm2) apart from being ineffi cient from economic point of view when applied to manycore technology [1, 2]. Moreover, the uneven workload on the cores leads to spatiotemporal non-uniformity in the thermal fi eld on chip which can be detrimental to its performance and reliability [3]. e leakage power also increases exponentially with temperature resulting in higher power dissipation, and cooling costs [4, 5]. Another way to obtain a uniform on-chip temperature distribution and lower peak temperature is effi cient redistribution of heat within the chip which can help to improve the energy effi ciency and coeffi cient of performance (~compute/cooling INTRODUCTION |
| File Format | PDF HTM / HTML |
| Alternate Webpage(s) | http://minds.gatech.edu/Publications/Papers_2013/217332-Electronics%20Co.pdf |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
