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Cache and Memory
| Content Provider | Scilit |
|---|---|
| Author | Jing, Chen Zhu, Heqing |
| Copyright Year | 2020 |
| Description | This chapter focuses on the cache, memory using non-Intel® platform based server platform as the hardware example. The computer system consists of cache, memory, and storage hardware modules for data process, movement, and storage. SRAM has much less latency than DRAM; it is more expensive, and has a small capacity and low power consumption; and it is heavily integrated within other chips such as CPU, field-programmable gate array, and network processor units. The cache coherence is handled by CPU since this reduces software complexity. In the computing system, software uses the virtual memory address, not the physical memory address. Memory management and paging technology has been widely used for address translation. Different processor architectures may support the different HugePage size. Book Name: Data Plane Development Kit (DPDK) |
| Related Links | https://content.taylorfrancis.com/books/download?dac=C2019-0-06078-1&isbn=9780429353512&doi=10.1201/9780429353512-3&format=pdf |
| Ending Page | 49 |
| Page Count | 19 |
| Starting Page | 31 |
| DOI | 10.1201/9780429353512-3 |
| Language | English |
| Publisher | Informa UK Limited |
| Publisher Date | 2020-11-19 |
| Access Restriction | Open |
| Subject Keyword | Book Name: Data Plane Development Kit (dpdk) Hardware and Architecturee Memory Address Computing System Hardware Platform Software Processor Storage |
| Content Type | Text |
| Resource Type | Chapter |
