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Improved performance of on chip communication fabric using different arbitration techniques
| Content Provider | Scilit |
|---|---|
| Author | Rao, A. Musala Venkateswara Hemanth, B. Kaja Razia, C. Shaik |
| Copyright Year | 2021 |
| Description | The Network on Chip (NoC) is an effective practice for the interfacing of Application on Chip (AoC)s in development of embedded architectures. The AoC uses various processors, embedded devices, and soft cores. Over the years, the demand for expertise in the implementation of efficient arbiters has increased due to the emerging of on-chip interconnections. Which requires low latency at the time of message transmission. The aim of the communication channel is to provide the better performance for the present scenario like increase in volume of processing elements. arbitrators are recommended for a fair outcome in NoC with minimal power, area, time, and router control paths consist of buffers, arbiters, and the allocators at every resource point. In this approach we proposed an arbiter with less power, area, and arbitration delay. Book Name: Recent Trends in Communication and Electronics |
| Related Links | https://api.taylorfrancis.com/content/chapters/edit/download?identifierName=doi&identifierValue=10.1201/9781003193838-40&type=chapterpdf |
| Ending Page | 216 |
| Page Count | 7 |
| Starting Page | 210 |
| DOI | 10.1201/9781003193838-40 |
| Language | English |
| Publisher | Informa UK Limited |
| Publisher Date | 2021-06-19 |
| Access Restriction | Open |
| Subject Keyword | Book Name: Recent Trends in Communication and Electronics Hardware and Architecturee Noc Aoc Arbiters Embedded Different Arbitration Various Processors Minimal Power Chip Communication |
| Content Type | Text |
| Resource Type | Chapter |
