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High-Speed Wide-Range True-Single-Phase-Clock CMOS Dual Modulus Prescaler
| Content Provider | MDPI |
|---|---|
| Author | Li, Xiaoran Gao, Jian Chen, Zhiming Wang, Xinghua |
| Copyright Year | 2020 |
| Description | This manuscript presents two novel low-power high-speed true-single-phase-clock (TSPC) prescalers with division ratios of 2/3 and 4/5, respectively, in a standard 90-nm CMOS technology. The logic gates incorporated between the D-flip-flops (DFFs) of a conventional 2/3 prescaler are modified to reduce the propagation delay and hence increase the maximum operating frequency. The measurement results show that the proposed divide-by-2/3 and divide-by-4/5 prescalers can operate up to 17 GHz and 15.3 GHz, respectively, which increase by 5.4 GHz and 4.3 GHz compared with conventional TSPC prescalers. The power of the proposed divide-by-2/3 prescaler is 0.67 mW and 0.92 mW, and 0.87 mW and 1.06 mW for the proposed divide-by-4/5 prescaler. The chip occupies an area of 20 × 35 μm2 and 20 × 50 μm2 for the proposed divide-by-2/3 and divide-by-4/5 prescalers. |
| Starting Page | 725 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics9050725 |
| Journal | Electronics |
| Issue Number | 5 |
| Volume Number | 9 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2020-04-28 |
| Access Restriction | Open |
| Subject Keyword | Electronics Hardware and Architecturee Cmos Frequency Divider High Speed Prescaler Propagation Delay True-single-phase-clock (tspc) |
| Content Type | Text |
| Resource Type | Article |
