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CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions
| Content Provider | MDPI |
|---|---|
| Author | Carlos, Arturo Hernández-Gracidas Monica, Amador García Medina-Santiago, Alejandro Morales-Rosales, Luis Alberto Algredo-Badillo, Ignacio Torres, Jorge Antonio Orozco |
| Copyright Year | 2021 |
| Description | The design of neural network architectures is carried out using methods that optimize a particular objective function, in which a point that minimizes the function is sought. In reported works, they only focused on software simulations or commercial complementary metal-oxide-semiconductor (CMOS), neither of which guarantees the quality of the solution. In this work, we designed a hardware architecture using individual neurons as building blocks based on the optimization of n-dimensional objective functions, such as obtaining the bias and synaptic weight parameters of an artificial neural network (ANN) model using the gradient descent method. The ANN-based architecture has a 5-3-1 configuration and is implemented on a 1.2 |
| Starting Page | 7071 |
| e-ISSN | 14248220 |
| DOI | 10.3390/s21217071 |
| Journal | Sensors |
| Issue Number | 21 |
| Volume Number | 21 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2021-10-25 |
| Access Restriction | Open |
| Subject Keyword | Sensors Cmos Circuit Analog System Signal Processing Learning Algorithm Artificial Neural Network |
| Content Type | Text |
| Resource Type | Article |
