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Recent Progress on 3D NAND Flash Technologies
| Content Provider | MDPI |
|---|---|
| Author | Goda, Akira |
| Copyright Year | 2021 |
| Description | Since 3D NAND was introduced to the industry with 24 layers, the areal density has been successfully increased more than ten times, and has exceeded 10 $Gb/mm^{2}$ with 176 layers. The physical scaling of XYZ dimensions including layer stacking and footprint scaling enabled the density scaling. Logical scaling has been successfully realized, too. TLC (triple-level cell, 3 bits per cell) is now the mainstream in 3D NAND, while QLC (quad-level cell, 4 bits per cell) is increasing the presence. Several attempts and partial demonstrations were made for PLC (penta-level cell, 5 bits per cell). CMOS under array (CuA) enabled the die size reduction and performance improvements. Program and erase schemes to address the technology challenges such as short-term data retention of the charge-trap cell and the large block size are being investigated. |
| Starting Page | 3156 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics10243156 |
| Journal | Electronics |
| Issue Number | 24 |
| Volume Number | 10 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2021-12-18 |
| Access Restriction | Open |
| Subject Keyword | Electronics 3d Nand Floating Gate Cell Charge-trap Cell Cmos Under Array |
| Content Type | Text |
| Resource Type | Article |
