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Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories
| Content Provider | MDPI |
|---|---|
| Author | Na, Taehui |
| Copyright Year | 2020 |
| Description | With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16. |
| Starting Page | 1403 |
| e-ISSN | 20799292 |
| DOI | 10.3390/electronics9091403 |
| Journal | Electronics |
| Issue Number | 9 |
| Volume Number | 9 |
| Language | English |
| Publisher | MDPI |
| Publisher Date | 2020-08-30 |
| Access Restriction | Open |
| Subject Keyword | Electronics Hardware and Architecturee Nonvolatile Memory (nvm) Offset Voltage Offset-canceling Dual-stage Sensing Circuit (ocds-sc) Read Yield Sense Amplifier (sa) Sensing Dead Zone Time-difference Inputs |
| Content Type | Text |
| Resource Type | Article |
