NDLI: Design of In-Memory Parallel-Prefix Adders

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Design of In-Memory Parallel-Prefix Adders

Content Provider	MDPI
Author	Reuben, John
Copyright Year	2021
Description	Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width ( $O(n)). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition inO(log(n)) latency in the memory array.$
Starting Page	45
e-ISSN	20799268
DOI	10.3390/jlpea11040045
Journal	Journal of Low Power Electronics and Applications
Issue Number	4
Volume Number	11
Language	English
Publisher	MDPI
Publisher Date	2021-11-24
Access Restriction	Open
Subject Keyword	Journal of Low Power Electronics and Applications Hardware and Architecturee Resistive Ram (reram) Non-volatile Memory (nvm) Majority Logic Memristor 1transistor-1resistor (1t–1r) In-memory Computing Processing-in-memory Parallel-prefix Adder Logic-in-memory Memristive Logic
Content Type	Text
Resource Type	Article

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