NDLI: Field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network

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Field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network

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Field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network

Content Provider	IET Digital Library
Author	Anumandla, Kiran Kumar Peesapati, Rangababu Sabat, Samrat L. Udgata, Siba K. Abraham, Ajith
Abstract	In this study, a scalable coprocessor for accelerating the Differential Evolution (DE) algorithm is presented. The coprocessor is interfaced with PowerPC embedded processor of Xilinx Virtex-5 FX70T Field Programmable Gate Array. In the proposed design, the DE algorithm module is tightly coupled with fitness function module to reduce communication and control overhead. The fixed point DE algorithm is implemented in the coprocessor whereas both fixed and floating point DE are implemented in the embedded processor. Performance of the coprocessor is evaluated by optimising benchmark functions of different complexities. The implementation results show that the coprocessor is 73.14–160.2× and 2.19–27.63× faster compared to the software execution time of the floating and fixed point algorithm respectively. As a case study, spectrum allocation problem of cognitive radio network is evaluated with the coprocessor. Results show an acceleration of 76.79–105× and 5.19–6.91× with respect to floating and fixed point DE in embedded processor. It is also observed that the application occupies 56% of BRAM, 54% of DSP48E, 16% of slice LUTs and maximum frequency of operation as 63.55 MHz in a Virtex-5 FPGA. This type of coprocessor is suitable for embedded applications where the fitness function remains unchanged.
Starting Page	221
Ending Page	234
Page Count	14
ISSN	17518601
Volume Number	7
e-ISSN	1751861X
Issue Number	Issue 5, Sep (2013)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/7/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2012.0109
Journal	IET Computers & Digital Techniques
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Cognitive Radio Cognitive Radio Network Coprocessor Development Coprocessors DE Algorithm Differential Evolution Coprocessor Digital Arithmetic Method Direct Software Execution Embedded Processor Embedded System Field Programmable Gate Array Fitness Function Evaluation Module Fixed Point Algorithm Floating Point Algorithm Floating Point Arithmetic Hardcore PowerPC Embedded Processor Logic And Switching Circuit Logic Circuit Microprocessor Chips Microprocessors And Microcomputer Radio Link And Equipment Scalable Coprocessor Spectrum Allocation Spectrum Allocation Problem Xilinx Virtex 5 Field Programmable Gate Array
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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