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Two-stage logarithmic converter with reduced memory requirements

Content Provider	IET Digital Library
Author	Chaudhary, Mandeep Lee, Peter
Abstract	This study presents an efficient method for converting a normalised binary number x (1 ≤ x < 2) into a binary logarithm. The algorithm requires less memory and fewer arithmetic components to achieve 23 bits of fractional precision than other algorithms using uniform and non-uniform piecewise linear or piecewise polynomial techniques and requires less than 20 kbits of ROM and a maximum of three multipliers. It is easily extensible to higher numeric precision and has been implemented on Xilinx Spartan3 and Spartan6 field programmable gate arrays (FPGA) to show the effect of recent architectural enhancements to the reconfigurable fabric on implementation efficiency. Synthesis results confirm that the algorithm operates at a frequency of 42.3 MHz on a Spartan3 device and 127.8 MHz on a Spartan6 with a latency of two clocks. This increases to 71.4 and 160 MHz, respectively, when the latency is increased to eight clocks. On a Spartan6 XC6SLX16 device, the converter uses just 55 logic slices, three multipliers and 11.3kbits of Block RAM configured as ROM.
Starting Page	23
Ending Page	29
Page Count	7
ISSN	17518601
Volume Number	8
e-ISSN	1751861X
Issue Number	Issue 1, Jan (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/8/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2012.0134
Journal	IET Computers & Digital Techniques
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Arithmetic Component Binary Logarithm Block RAM Computer Architecture Converter Digital Arithmetic Method Field Programmable Gate Array Fractional Precision Frequency 127.8 MHz Frequency 160 MHz Frequency 42.3 MHz Frequency 71.4 MHz Logic And Switching Circuit Logic Circuit Logic Slices Memory Circuit Multipliers Nonuniform Piecewise Linear Technique Nonuniform Piecewise Polynomial Technique Normalised Binary Number Conversion Numeric Precision Piecewise Linear Technique Piecewise Polynomial Technique Read-only Storage Reconfigurable Architectures Reconflgurable Fabric Reduced Memory Requirements ROM Semiconductor Storage Spartan6 XC6SLX16 Device Storage Capacity 11.3 Kbit Two-stage Logarithmic Converter Uniform Piecewise Linear Technique Uniform Piecewise Polynomial Technique Xilinx Spartan 3 FPGA Xilinx Spartan 6 FPGA
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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