NDLI: Enumeration technique in very large-scale integration fixed-outline floorplanning

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Enumeration technique in very large-scale integration fixed-outline floorplanning

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Enumeration technique in very large-scale integration fixed-outline floorplanning

Content Provider	IET Digital Library
Author	Hoo, Chyi Shiang Kanesan, Jeevan Ramiah, Harikrishnan
Abstract	Even though enumeration is a common technique adapted in very large-scale integration (VLSI) floorplanning, its impact in terms of wirelength, whitespace, as well as runtime on the floorplanning has never been investigated comprehensively. In this study, enumerative floorplanner (EFP) is proposed here by using enumeration. The impact of the maximum enumeration order on VLSI floorplan layout is investigated and the tradeoff relationship with the wirelength, area and runtime is analysed as well. In EFP, dynamic programming enumerative clustering (DEC) technique is employed to reduce the worst-case time complexity and runtime. DEC also introduces the same number of possible permutations of modules while reducing the redundancy created in enumerative clustering (EC) without the usage of dynamic programming. A straightforward cost function is adapted to assist DEC to select the best cluster permutation, and a rigorous local refinement is proposed to compensate the EC's impact on the floorplan wirelength. Experimental results show that EFP is a high performance floorplanner when compared to existing methods in terms of robustness, scalability and stability.
Starting Page	47
Ending Page	57
Page Count	11
ISSN	1751858X
Volume Number	8
e-ISSN	17518598
Issue Number	Issue 1, Jan (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/8/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2013.0003
Journal	IET Circuits, Devices & Systems
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Circuit Stability Cluster Permutation Costing DEC Technique Dynamic Programming Dynamic Programming Enumerative Clustering Technique EFP Enumerative Floorplanner Integrated Circuit Layout Layout Modelling And Testing Optimisation Technique Pattern Clustering Rigorous Local Refinement Semiconductor Integrated Circuit Design Stability Straightforward Cost Function Time Complexity Very Large-scale Integration Fixed-outline Floorplanning VLSI VLSI Floorplan Layout WhiteSpace Wirelength
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

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