NDLI: Improved matrix multiplier design for high-speed digital signal processing applications

Please wait, while we are loading the content...

Biosurface and Biotribology

CAAI Transactions on Intelligence Technology

CIRED - Open Access Proceedings Journal

Chinese Journal of Electronics

Cognitive Computation and Systems

Electronics Letters

Energy Conversion and Economics

Engineering & Technology

Engineering Biology

Healthcare Technology Letters

IET Circuits, Devices & Systems

Volume 15 (2021)

Volume 14 (2020)

Volume 13 (2019)

Volume 12 (2018)

Volume 11 (2017)

Volume 10 (2016)

Volume 9 (2015)

Volume 8 (2014)

Volume 8 (2014) : Issue 6, Nov

Volume 8 (2014) : Issue 5, Sep

Volume 8 (2014) : Issue 4, Jul

Volume 8 (2014) : Issue 3, May

Volume 8 (2014) : Issue 2, Mar

Volume 8 (2014) : Issue 1, Jan

Analytical model for CMOS cross-coupled LC-tank oscillator

Digital delay locked loop-based frequency synthesiser for Digital Video Broadcasting-Terrestrial receivers

Enumeration technique in very large-scale integration fixed-outline floorplanning

Improved matrix multiplier design for high-speed digital signal processing applications

On-chip readout circuit for nanomagnetic logic

Resilience and yield of flip-flops in future CMOS technologies under process variations and aging

Timing variation aware dynamic digital phase detector for low-latency clock domain crossing

VLSI implementation of high-throughput parallel H.264/AVC baseline intra-predictor

Volume 7 (2013)

Volume 6 (2012)

Volume 5 (2011)

Volume 2 (2008)

Volume 1 (2007)

IET Collaborative Intelligent Manufacturing

IET Communications

IET Computer Vision

IET Computers & Digital Techniques

IET Control Theory & Applications

IET Cyber-Physical Systems: Theory & Applications

IET Cyber-Systems and Robotics

IET Electric Power Applications

IET Electrical Systems in Transportation

IET Energy Systems Integration

IET Generation, Transmission & Distribution

IET Image Processing

IET Information Security

IET Intelligent Transport Systems

IET Microwaves, Antennas & Propagation

IET Nanobiotechnology

IET Nanodielectrics

IET Optoelectronics

IET Power Electronics

IET Quantum Communication

IET Radar, Sonar & Navigation

IET Renewable Power Generation

IET Science, Measurement & Technology

IET Signal Processing

IET Smart Cities

IET Systems Biology

IET Wireless Sensor Systems

Micro & Nano Letters

The Journal of Engineering

Improved matrix multiplier design for high-speed digital signal processing applications

Content Provider	IET Digital Library
Author	Saha, Prabir Banerjee, Arindam Bhattacharyya, Partha Dandapat, Anup
Abstract	A transistor level implementation of an improved matrix multiplier for high-speed digital signal processing applications based on matrix element transformation and multiplication is reported in this study. The improvement in speed was achieved by rearranging the matrix element into a two-dimensional array of processing elements interconnected as a mesh. The edges of each row and column were interconnected in torus structure, facilitating simultaneous implementation of several multiplications. The functionality of the circuitry was verified and the performance parameters for example, propagation delay and dynamic switching power consumptions were calculated using spice spectre using 90 nm CMOS technology. The proposed methodology ensures substantial reduction in propagation delay compared with the conventional algorithm, systolic array and pseudo number theoretic transformation (PNTT)-based implementation, which are the most commonly used techniques, for matrix multiplication. The propagation delay of the implemented 4 × 4 matrix multiplier was only ∼2 µs, whereas the power consumption of the implemented 4 × 4 matrix multiplier was ∼3.12 mW only. Improvement in speed compared with earlier reported matrix multipliers, for example, conventional algorithm, systolic array and PNTT-based implementation was found to be ∼67, ∼56 and ∼65%, respectively.
Starting Page	27
Ending Page	37
Page Count	11
ISSN	1751858X
Volume Number	8
e-ISSN	17518598
Issue Number	Issue 1, Jan (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/8/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2013.0117
Journal	IET Circuits, Devices & Systems
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Algebra CMOS Integrated Circuit CMOS Technology Delay Digital Signal Processing Chips Dynamic Switching Power Consumption High-speed Digital Signal Processing Application Matrix Element Transformation Matrix Multiplication Matrix Multiplier Design PNTT-based Implementation Power Consumption Propagation Delay Pseudo Number Theoretic Transformation-based Implementation Size 90 Nm Spice Spectre Substantial Reduction Systolic Array Torus Structure Transistor Level Implementation Two-dimensional Array
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in