NDLI: Single Fully Differential Second Generation Current Conveyor Based Four-Quadrant Analog Multiplier Design and Its Applications

Content Provider	IET Digital Library
Author	Roy, Suvajit Pal, Radha Raman
Abstract	This manuscript presents a new fourquadrant analog multiplier using a recently reported current mode active building block, namely the Fully differential second generation current conveyor (FDCCII). The proposed circuit employs single FDCCII and two NMOSFETs only, thus has simple architecture. It is fully-integrable as no other external passive component has been used. Non-ideal behaviour of the reported configuration has been analysed considering current and voltage tracking errors of the FDCCII. Workability of the derived multiplier is verified with PSPICE (Cadence 16.6) simulations using model parameter of TSMC 0:35μm CMOS process and found to be in close agreement with theoretical anticipations. The static power consumption of the circuit is 0.107mW. The circuit works well with good linearity (nonlinearity error ≤ 0:96%) for the input voltage range of ±0.5V for a supply voltage of ±1V and the output is insensitive to temperature variation. Simulation results show that the -3dB bandwidth of the proposed multiplier is 20.67MHz and the output referred noise is less than 9 nV / H z at 1kΩ load condition. MonteCarlo analysis has also been performed for the proposed configuration. The applicability of the reported multiplier as amplitude modulator, squarer, and frequency doubler are also demonstrated.
Starting Page	959
Ending Page	965
Page Count	7
ISSN	10224653
Volume Number	29
e-ISSN	20755597
Issue Number	Issue 5, Sep (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/cje/29/5
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/cje.2020.08.012
Journal	Chinese Journal of Electronics
Publisher Date	2020-09-01
Access Restriction	Open
Rights Holder	© Chinese Institute of Electronics
Subject Keyword	Active Filter Active Network Analogue Circuit Design Analogue Multipliers Analogue Processing Circuit Bandwidth 20.67 MHz CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Process Current Conveyors Current Mode Active Building Block Current Voltage Tracking Error Current-mode Circuit Derived Multiplier Electrical/electronic Equipment Energy Utilisation Four-quadrant Analog Multiplier Design Input Voltage Range Integrated Circuit Design Low Power Electronics Modelling Monte Carlo Method Monte-Carlo Analysis NMOSFET Nonideal Behaviour Power 0.107 MW Probability Theory Single FDCCII Single Fully Differential Second Generation Current Conveyor Size 0.35 Mum Spice Statistics Stochastic Linearised SCUC Testing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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