NDLI: 65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography

Content Provider	IET Digital Library
Author	Asif, Shahzad Andersson, Oskar Rodrigues, Joachim Kong, Yinan
Abstract	Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs.
Starting Page	62
Ending Page	67
Page Count	6
ISSN	17518601
Volume Number	12
e-ISSN	1751861X
Issue Number	Issue 2, Mar (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/12/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2017.0017
Journal	IET Computers & Digital Techniques
Publisher Date	2017-11-07
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	40-channel RNS Moduli-set 65-nm CMOS Low-energy RNS Modular Multiplier ASIC Chinese Remainder Theorem CMOS Integrated Circuit CMOS Logic Circuit Cryptography Data Security Digital Arithmetic Method Elliptic Curve Point Multiplication Elliptic-curve Cryptography Algorithm Energy Dissipation Energy-efficient ECC Logic And Switching Circuit Logic Circuit Low-voltage ECC Modular Exponentiation Modular Multiplication Multiplying Circuit Public Key Cryptography Residue Number System Rivest-Shamir-Adleman Cryptography Algorithm Short-channel Width
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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