NDLI: Test data compression using hierarchical block merging technique

Content Provider	IET Digital Library
Author	Vohra, Harpreet Singh, Amardeep
Abstract	Manufacturing of semiconductor devices at the sub-micron level has led to the introduction of huge number of faults. To ensure the quality of integrated circuits (ICs), enormous amount of test data is needed which, in turn, increases the overall test cost of the ICs. This study presents a hierarchical block-merging-based technique (HBMT) for test data compression, which appropriately encodes the test pattern blocks of fixed sizes at inter- and intra-block levels using lesser number of bits. The proposed technique works in four steps: segmentation of the entire length of test data into equal length blocks; categorisation of test blocks as compatible blocks and unique blocks; merging of compatible blocks to form representative pattern block, which is further merged at sub-block level; and compression of the non-compatible (unique) blocks using different encoding cases. Experimental results performed on various international symposium for circuits and systems (ISCAS)’ 89 benchmark circuits demonstrate the effectiveness of the proposed test data compression technique. It is found that application of HBMT can improve the compression efficiency by an average of 73% along with a reduction in the test application time. This study also presents the decoder architecture.
Starting Page	176
Ending Page	185
Page Count	10
ISSN	17518601
Volume Number	12
e-ISSN	1751861X
Issue Number	Issue 4, Jul (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/12/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2017.0045
Journal	IET Computers & Digital Techniques
Publisher Date	2018-02-14
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Data Compression Data Handling Technique Decoder Architecture HBMT Hierarchical Block Merging Technique Integrated Circuit Quality ISCAS 89 Benchmark Circuit Merging Semiconductor Device Manufacturing Test Blocks Categorisation Test Data Compression Test Data Segmentation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

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