NDLI: Vulnerability modelling of crypto-chips against scan-based attacks

Content Provider	IET Digital Library
Author	Taherifard, Mohammad Patooghy, Ahmad Fazeli, Mahdi
Abstract	In this study, a gate-level vulnerability model is proposed to detect the potential security holes of crypto-chips against scan-based attacks. The proposed model offers a relative measure so-called vulnerability factor (VF) for each net of a given crypto-chip. Nets with the highest VFs are considered as the most vulnerable nets of the crypto-chip. The VF of each gate output is calculated considering (i) VFs of the gate inputs, and (ii) the probability of having a signal transition at the gate output. In order to validate the proposed model, the authors implemented the iterative and pipelined AES, as well as the iterative DES encryption algorithms to find their most vulnerable nets. Then the most vulnerable nets of each design, have been masked by a simple mechanism to explore the accuracy of the proposed model. Results of scan-based attacks which are done by ModelSim simulations show that by masking only 32, 64 and 32 nets in iterative Advanced Encryption Standard (AES), pipelined AES and iterative Data Encryption Standard(DES) designs, respectively, all of the done attacks are failed. Achieved results of the proposed model in comparison with the signal activity and random approaches demonstrate the superiority of the proposed model.
Starting Page	543
Ending Page	550
Page Count	8
ISSN	17518709
Volume Number	12
e-ISSN	17518717
Issue Number	Issue 6, Nov (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ifs/12/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ifs.2017.0440
Journal	IET Information Security
Publisher Date	2018-04-04
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Crypto-chips Cryptography Data Security Gate Input Gate Output Gate-level Vulnerability Model Interpolation And Function Approximation Iterative Advanced Encryption Standard Iterative Data Encryption Standard Designs Iterative DES Encryption Algorithm Iterative Method Modelim Simulations Numerical Analysis Scan-based Attack Security Holes VF Vulnerability Factor Vulnerability Modelling Vulnerable Nets
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Information Systems Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Scan-based attack tolerance with minimum testability loss: a gate-level approach

Statistical security analysis of AES with X-tolerant response compactor against all types of test infrastructure attacks with/without novel unified countermeasure

Does stream cipher-based scan chains encryption really prevent scan attacks?

Does stream cipher-based scan chains encryption really prevent scan attacks?

The First 10 Years of Advanced Encryption

Stream vs Block ciphers for scan encryption

High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

Stream cipher-based scan encryption in test standards

Secure Scan: A Design-for-Test Architecture for Crypto Chips

Vulnerability modelling of crypto-chips against scan-based attacks

Similar Documents

Scan-based attack tolerance with minimum testability loss: a gate-level approach

Statistical security analysis of AES with X-tolerant response compactor against all types of test infrastructure attacks with/without novel unified countermeasure

Does stream cipher-based scan chains encryption really prevent scan attacks?

Does stream cipher-based scan chains encryption really prevent scan attacks?

The First 10 Years of Advanced Encryption

Stream vs Block ciphers for scan encryption

High-Throughput and Area-Efficient FPGA Implementations of Data Encryption Standard (DES)

Stream cipher-based scan encryption in test standards

Secure Scan: A Design-for-Test Architecture for Crypto Chips

Vulnerability modelling of crypto-chips against scan-based attacks