NDLI: Modification and hardware implementation of cortex-like object recognition model

Content Provider	IET Digital Library
Author	Anbaran, Alireza Mohammadi Torkzadeh, Pooya Ebrahimpour, Reza Bagheri, Nasour
Abstract	Object recognition in the visual cortex of mammals and humans has inspired many computational object recognition models. Hierarchical model and X (HMAX) is a well-known biologically motivated object recognition model with scale and position tolerance and high accuracy. Due to the computational intensive nature, hardware implementation with massive parallel processing is suggested for real-time applications. However, it is important to explore algorithmic trade-offs when mapping an algorithm to are configurable hardware. A direct conversion of the software implementation of an algorithm generally results inefficient hardware resource usage. In this study, the authors propose a novel modification into the HMAX model which makes it suitable for hardware implementation. More precisely, to reduce the number of memory blocks and multipliers of the S2 layer of HMAX produces, they replace the first norm by the second norm, which critically affects the silicon area in an application-specific integrated circuit implementation or the required resources in field-programmable gate array (FPGA). To evaluate the proposed model, they implement a pipelined version of the revised model on a mid-range commercial Xilinx FPGA, i.e. XC6VLX240T platform from a Virtex 6 family of Xilinx using ISE. Compared to the recent hardware implementation of HMAX, the proposed model offers 83% resource degradation in DSP48 slices and 3% in memory blocks.
Starting Page	3490
Ending Page	3498
Page Count	9
ISSN	17519659
Volume Number	14
e-ISSN	17519667
Issue Number	Issue 14, Dec (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-ipr/14/14
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-ipr.2019.0264
Journal	IET Image Processing
Publisher Date	2020-09-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Application-specific Integrated Circuit Implementation Biologically Motivated Object Recognition Model Computational Intensive Nature Computational Object Recognition Model Computer Vision And Image Processing Technique Configurable Hardware Cortex-like Object Recognition Model Field Programmable Gate Array Field-programmable Gate Array FPGA Hardware Implementation Hardware Resource Usage Hierarchical Model HMAX Model Image Recognition ISE Logic And Switching Circuit Logic Circuit Massive Parallel Processing Object Recognition Position Tolerance Software Implementation Virtex 6 Family Visual Cortex XC6VLX240T Platform Xilinx
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Vision and Pattern Recognition Software

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