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| Content Provider | IET Digital Library |
|---|---|
| Author | Garg, L. Sahula, V. |
| Abstract | Presented is the error that occurs while estimating subthreshold leakage power of parallel transistor stacks in CMOS gates using leakage power models when there is no consideration of the manufacturing variations, i.e. device geometry related effects in width. For the purpose, efficient support vector machine based macromodels for characterising the transistor stacks of CMOS gates are reported, considering process parameter variations impacting e.g. length, threshold voltage, oxide thickness, supply voltage, temperature and width of the transistors. The experiments show that maximum error can go up to ∼ 15% for AOI22 and OAI22 gate under nominal values of varying parameters without considering manufacturing variations in the width. |
| Starting Page | 644 |
| Ending Page | 646 |
| Page Count | 3 |
| ISSN | 00135194 |
| Volume Number | 49 |
| e-ISSN | 1350911X |
| Issue Number | Issue 10, May (2013) |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/el/49/10 |
| Alternate Webpage(s) | https://digital-library.theiet.org/content/journals/10.1049/el.2012.4311 |
| Journal | Electronics Letters |
| Access Restriction | Open |
| Rights Holder | © The Institution of Engineering and Technology |
| Subject Keyword | CMOS Gates CMOS Integrated Circuit CMOS Subthreshold Leakage Analysis Electronic Engineering Computing Knowledge Engineering Technique Leakage Power Model Parallel Transistor Stacks Parameter Variations Stack Based Model Support Vector Machine Transistor Circuit |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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