NDLI: 55 dB DC gain, robust to PVT single-stage fully differential amplifier on 45 nm SOI-CMOS technology

Content Provider	IET Digital Library
Author	Gómez, H. Espinosa, G.
Abstract	The design of a single-stage operational transconductance amplifier is presented, which uses self-cascode transistors and current shunt stages to improve its DC gain. The proposed amplifier is implemented in a standard 45 nm silicon on insulator CMOS process. Simulation results show that the amplifier has a DC gain above 50 dB despite physical and environmental variations with a minimum gain bandwidth product of 540 MHZ and more than 55° phase margin. In addition, the simulated transient behaviour is shown to be robust, with a slew rate of 500 V/μs and a settling time of 7 ns with 1% accuracy for a C L of 0.3 pF.
Starting Page	737
Ending Page	739
Page Count	3
ISSN	00135194
Volume Number	50
e-ISSN	1350911X
Issue Number	Issue 10, May (2014)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/50/10
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.0883
Journal	Electronics Letters
Publisher Date	2014-05-02
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Amplifiers Bandwidth 540 MHz Capacitance 0.3 PF CMOS Analogue Integrated Circuit CMOS Integrated Circuit Current Shunt Stage Differential Amplifiers Elemental Semiconductor Gain 55 DB GBW Product Integrated Circuit Design Layout Microwave IC Minimum Gain Bandwidth Product Modelling And Testing Operational Amplifier Phase Margin PM PVT Single-stage Fully Differential Amplifier Self-cascode Transistor Semiconductor Integrated Circuit Design Silicon Silicon on Insulator Silicon-on-insulator Simulated Transient Behaviour Single-stage Operational Transconductance Amplifier Size 45 Nm Slew Rate SOI-CMOS Technology Time 7 Ns UHF Amplifiers UHF Integrated Circuit
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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