NDLI: Self-biased anti-parallel diode pair in 130-nm CMOS

Content Provider	IET Digital Library
Author	Shim, D. O, K. K.
Abstract	This Letter presents a self-biased anti-parallel diode pair (APDP) in a 130-nm standard digital CMOS process. The proposed device employs complementary polysilicon-gate-separated Schottky barrier diodes (SBDs). A parallel RC network in series with the n-well of n-type SBD connected in shunt is used to build-up the self-bias voltage that depends on the input power level. The device exhibits less roll-off in output harmonic power generation at a high input power level due to the automatic adjustment of the I–V curve. The measured cutoff frequency of the device reaches ∼530 GHz at zero-bias. Harmonic power measurements indicate that use of the self-biasing reduces saturation at high input power levels. The self-biased complementary-APDP (C-APDP) generates up to 5.7 dB higher third harmonic power than the cathode-tied C-APDP.
Starting Page	1147
Ending Page	1149
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 13, Jun (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/13
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.1075
Journal	Electronics Letters
Publisher Date	2016-05-16
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Cathode-tied C-APDP CMOS Digital Integrated Circuit CMOS Integrated Circuit Complementary Polysilicon-gate-separated Schottky Barrier Diodes Cutoff Frequency Harmonic Power Measurement I-V Curve Input Power Level Junction And Barrier Diode N-type SBD Output Harmonic Power Generation Parallel RC Network RC Circuit SBDs Schottky Diode Self-bias Voltage Self-biased Anti-parallel Diode Pair Self-biased Complementary-APDP Size 130 Nm Standard Digital CMOS Process
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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