NDLI: Reliable NoC design with low latency and power consumption

Content Provider	IET Digital Library
Author	Yan, Fengxia Gao, Jianliang
Abstract	Reliability has become one of the most crucial issues in network-on-chip (NoC). But how to keep low latency and power consumption when achieving reliability is still a curial challenge. A novel scheme for reliable NoCs is proposed. In the scheme, header flit is protected from router to router and data is protected from end to end. To implement the scheme, a new header protection buffer in routers is designed, which can check the timing errors and tolerate the soft errors simultaneously. Instead of checking on each router, data packet is only decoded and checked on receiver's network interface. In this way, the scheme ensures reliable transmission with low latency and power consumption. Experimental results show the feasibility of the proposed scheme in terms of power consumption, latency and area cost.
Starting Page	382
Ending Page	383
Page Count	2
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 6, Mar (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/6
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.4665
Journal	Electronics Letters
Publisher Date	2017-02-08
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Data Packet Data Protection Digital Circuit Design, Modelling And Testing End to End Data Protection Header Protection Buffer Integrated Circuit Design Integrated Circuit Reliability Low Power Electronics Network Interface Network Routing Network-on-chip Power Consumption Radiation Hardening (electronics) Reliability Reliable NoC Design Router Soft Error Timing Error
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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