NDLI: Triple epitaxial single-photon avalanche diode for multichannel timing applications

Content Provider	IET Digital Library
Author	Labanca, I. Ceccarelli, F. Gulinatti, A. Ghioni, M. Rech, I.
Abstract	In the last years, custom-technology single-photon avalanche diodes (SPADs) have demonstrated remarkable performance, thanks to the fine engineering process performed on the electric field profile. However, the integration of custom SPADs in detector arrays often conflicts with the low-threshold current sensing that is mandatory to extract the timing information. A new custom-technology SPAD is introduced, that exploits an extra epitaxial layer in order to reduce the capacitive coupling between the anode and the chip substrate. The new detector shows a state-of-the-art timing jitter of 34 ps full width at half maximum and a weak dependence on the detection threshold, even when the substrate is kept at a fixed voltage, as required by the implementation of multichannel photon timing systems.
Starting Page	644
Ending Page	645
Page Count	2
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 10, May (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/10
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.0692
Journal	Electronics Letters
Publisher Date	2018-04-09
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Anode Avalanche Photodiode Bolometers Capacitive Coupling Chip Substrate Custom-technology Single-photon Avalanche Diodes Custom-technology SPAD Detection of Radiation Detector Array Electric Field Profile Extra Epitaxial Layer III-V SemiConductor Integrated Optics Integrated Optoelectronics Low-threshold Current Sensing Multichannel Photon Multichannel Timing Application PhotoDetector Photoelectric Cell Photoelectric Device Photon Counting State-of-the-art Timing Jitter Submillimetre Wave Detection Time 34.0 Ps Timing Information Timing Jitter Triple Epitaxial Single-photon Avalanche Diode
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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