NDLI: Secure memristor replicator architecture with physical uncloneability

Content Provider	IET Digital Library
Author	Yang, X. Khandelwal, S. Jabir, A.
Abstract	A lightweight and highly versatile architecture for replicating the resistance of a source memristor into a destination memristor is presented. This can be useful for storing or backing up sensed analogue information, e.g. sensed resistance, voltage, etc. in a single memristor. The architecture, which is simple and power efficient, is also able to produce non-linear digital codes during the replication process for added security by taking advantage of the non-linear behaviour of memristors. The generated codes can also be used to retrieve the analogue value within acceptable conversion errors, with circuit elements already built into the replicator. The authors also show that the architecture demonstrates physical uncloneable properties.
Starting Page	1275
Ending Page	1277
Page Count	3
ISSN	00135194
Volume Number	55
e-ISSN	1350911X
Issue Number	Issue 24, Nov (2019)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/55/24
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2019.1538
Journal	Electronics Letters
Publisher Date	2019-10-11
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Code Conversion Error Destination Memristor Lightweight Architecture Memristors Nonlinear Behaviour Nonlinear Code Nonlinear Digital Code Physical Uncloneability Physical Uncloneable Property Replication Process Resistor Secure Memristor Replicator Architecture Sensed Resistance Single Memristor Source Memristor
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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