NDLI: Block Aging Prevention technique (BAP) for flash based Solid State Disks

Content Provider	IEEE Xplore Digital Library
Author	Shiraz, S. Zaman, A. Zia, S. Mansoor, A. Ahmed, F.
Copyright Year	2011
Description	Author affiliation: School of Electrical Engineering and Computer Science (SEECS), National University of Science and Technology (NUST), Pakistan (Shiraz, S.; Zaman, A.; Zia, S.; Mansoor, A.; Ahmed, F.)
Abstract	Solid State Disks (SSDs) are becoming increasingly popular due to enhancement in speed and reduction in size, power and cost. It is an obvious choice for many applications including personal computers, embedded systems, medical and healthcare devices etc. However, the reliability of SSD has now become a critical issue and this is an area of active research. SSD uses Flash technology which is a fast, efficient nonvolatile storage chip and offers cost-effective solution for SSDs. However, with all these features, flash memory defines a limit of write-erase on its blocks. Wearleveling policies extend SSD life time by ensuring even wearleveling of the blocks in a flash memory. Several algorithms have been proposed to improve wearleveling of SSD including Hot-Cold Swapping, Dual pool Algorithm (DP), Kim and Lee algorithm (KL) and Cost Age and Times Algorithm (CAT). This paper discusses all these wearleveling policies and introduces a Block Aging Prevention (BAP) technique which has been tested on 8Gb Flash. The comparison of all these algorithms show that the proposed technique has reduced the erasure count deviation of NAND flash blocks by 6.71% and 20% compared to DP and CAT respectively. It has also reduced overhead by 4% comparatively to DP.
Starting Page	1
Ending Page	6
File Size	1511595
Page Count	6
File Format	PDF
ISBN	9781457707698
e-ISBN	9781457707681
DOI	10.1109/ICET.2011.6048453
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-05
Publisher Place	Pakistan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Nonvolatile memory Wearleveling Flash memory SSD Aging Solids Cleaning Flash Sorting FTL
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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