NDLI: CAST: A page-level FTL with compact address mapping and parallel data blocks

Content Provider	IEEE Xplore Digital Library
Author	Zhiyong Xu Ruixuan Li Cheng-Zhong Xu
Copyright Year	2012
Description	Author affiliation: School of Computer Science and Technology, Huazhong University of Science and Technology, China (Ruixuan Li) \|\| Shenzhen Institute of Advanced Technology, Chinese Academy of Science, China (Zhiyong Xu; Cheng-Zhong Xu)
Abstract	NAND flash memory based Solid State Drive (SSD) is increasingly popular as one of the major non-volatile storage devices. Due to the superior performance and energy efficiency properties, it becomes an important complimentary device between the main memory and the traditional mechanical Hard Disk Drive (HDD). It is also anticipated to substitute HDD as the mainstream secondary storage. Today, flash memory is widely used in embedded systems, hand-held devices, personal computers and even enterprise computer systems. To access the data on the flash, a software component called Flash Translation Layer (FTL) has to be applied to convert the file system logical address into the corresponding physical address. FTL has great impacts on the system overall performance. Numerous FTL algorithms have been proposed in the past decade. DFTL is one of the most popular page-level address mapping FTL algorithms. It has been considered to have the best flexibility. However, it has extra mapping information I/O overhead and cannot always achieve the optimal performance. In this paper, we propose CAST, a novel and efficient pagelevel FTL algorithm to relieve this issue. CAST reserves a small portion of embedded SRAM to cache most recently accessed logical-physical address mapping information. Unlike DFTL, we use a compact packing methodology. Consecutive logical-physical page mapping information is represented with only a single entry. Thus, more address mapping information can be maintained in the caching table, and the cache hit rates can be increased. To improve the garbage collection efficiency, CAST maintains multiple current data blocks simultaneously. When a new data write request comes, the system can select an appropriate one to conduct the process based on the request issuer and/or logical address information. Our simulation results show that CAST outperforms DFTL under various workloads and it can reduce the number of erase operations and decrease the I/O response time significantly.
Starting Page	142
Ending Page	151
File Size	442828
Page Count	10
File Format	PDF
ISBN	9781467348812
ISSN	10972641
e-ISBN	9781467348836
DOI	10.1109/PCCC.2012.6407747
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ash Random access memory Portable computers Algorithm design and analysis Data structures Flash memory Demand-based FTL (DFTL) NAND flash memory Solid-State Drive (SSD) SingleLevel Cell (SLC) Multi-Level Cell (MLC) Flash Translatio Layer (FTL)
Content Type	Text
Resource Type	Article

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