NDLI: Minimizing the Output Voltage Ripple of a DC/DC Power Converter by Phase Locking

Content Provider	IEEE Xplore Digital Library
Author	Upadhyaya, Prabal Hess, Herbert L.
Copyright Year	2007
Description	Author affiliation: Mieroelectronics Research and Communications Institute (MRCI), Department of Electrical and Computer Engineering, University of Idaho, Moscow, Idaho 83844, Prabal.upadhyaya@vandals.uidaho.edu (Upadhyaya, Prabal) \|\| Mieroelectronics Research and Communications Institute (MRCI), Department of Electrical and Computer Engineering, University of Idaho, Moscow, Idaho 83844 (Hess, Herbert L.)
Abstract	Reduced passives size and improved quality factor (Q) for an on-chip inductor can be achieved in a fully integrated DC/DC power converter by high frequency switching. This paper presents a high speed closed-loop buck converter that uses phase locking control system to reduce output voltage ripple. A closed-loop DC/DC power converter has been designed in a TSMC-0.25¿m technology. The power converter takes a 3.3 V DC input and switches at 1.02 GHz to produce output voltage of 1.5 V and 1.8 V DC and stabilizes in less than 600 ns. Design equations and simulation results are presented.
Starting Page	31
Ending Page	34
File Size	3173320
Page Count	4
File Format	PDF
ISBN	1424411130
DOI	10.1109/WMED.2007.368052
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switching converters Buck converters On-chip DC/DC power Converter Q factor Capacitors high frequency Switches Pulse width modulation Frequency conversion phase locking Inductors Pulse width modulation converters Voltage
Content Type	Text
Resource Type	Article

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