NDLI: Evaluation of solder-to-passivation attachment as a wafer bumping architecture: I. Insulating properties

Content Provider	IEEE Xplore Digital Library
Author	Harvey, I.R. Larsen, M.R. Turner, D. Doyle, I. Somers, J. Ortowski, J.
Copyright Year	2004
Description	Author affiliation: Dept. of Mech. Eng., Utah Univ., Salt Lake City, UT, USA (Harvey, I.R.; Larsen, M.R.)
Abstract	This paper describes the concept of direct mechanical attachment of a solder bump to the base IC passivation, in what has been called "wide via" design - a low-cost design option rejected for use by Bourns. In general use over an ASIC or other active device, this architecture relies upon the oxide/nitride passivation stack for complete conformal coverage of IC routing metalization, and assumes an absence of pinholes. We have created a test chip to evaluate the validity of these assumptions under BHT testing, as well as to enable comparative thermomechanical performance and induced parasitic effects. In this paper, we describe the BHT and failure analysis results indicating that passivation processes need to be optimized in order for this architecture to work. This result has implications in "over-the-fence" design in which a bump supplier makes assumptions regarding the quality of passivation from an IC manufacturer, and how passivation stacks which were good enough for peripheral wire bonding applications may need to be re-thought for area-array bumping.
Starting Page	103
Ending Page	107
File Size	1517510
Page Count	5
File Format	PDF
ISBN	0780383699
DOI	10.1109/WMED.2004.1297364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Insulation Thermomechanical processes Failure analysis Routing Manufacturing Wire Bonding Passivation Testing
Content Type	Text
Resource Type	Article

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