NDLI: VLSI implementation of Inverse Discrete Wavelet Transform for JPEG 2000

Content Provider	IEEE Xplore Digital Library
Author	Bhuyan, M.S. Amin, N. Madesa, M.A.H. Islam, M.S.
Copyright Year	2007
Description	Author affiliation: Fac. of Eng., Multimedia Univ., Cyberjaya (Bhuyan, M.S.)
Abstract	This paper presents hardware design flow of the inverse discrete wavelet transform (IDWT) core which is the second-most computationally intensive block in JPEG 2000 image compression standard. Lifting scheme (LS) is implemented in designing the IDWT hardwire module that reduces the number of execution steps involved in computation to almost one-half of those needed with a conventional convolution approach. In addition, the LS is amenable to ldquoin-placerdquo computation, so that the IDWT can be implemented in low memory systems. The IDWT module does not comprise any hardware multiplier unit and therefore suitable for development of high performance image processor. The IDWT module has been developed in VHDL using Quartus II from Altera. The VHDL model is validated through simulation using ModelSim-Altera. Simulation results show the IDWT module can perform three levels inverse transform on a 256times256 forward transformed image in 8.7 ms. Latency of the system is calculated 50 ns and the power dissipation by the device is 662 mW. The IDWT module consumes just 57 combinational ALUTs and 60 logic registers of a Stratix II device, and runs at 300 MHz clock frequency, reaches a speed performance suitable for several real-time applications. Throughput in terms of input coefficients processed per second of the IDWT core is 7.13Msamples. The motivation in designing is to reduce its complexity, enhance its performance and to make it suitable development on a reconfigurable FPGA based platform for VLSI implementation.
Starting Page	1
Ending Page	5
File Size	2085513
Page Count	5
File Format	PDF
ISBN	9781424415502
DOI	10.1109/ICCITECHN.2007.4579438
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-27
Publisher Place	Bangladesh
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DWT JPEG 2000 FPGA Image transforms
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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VLSI implementation of Inverse Discrete Wavelet Transform for JPEG 2000

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