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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Singh, I.V. Alam, M.S. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electron. Eng., Aligarh Muslim Univ., Aligarh, India (Singh, I.V.; Alam, M.S.) |
| Abstract | This work presents the linearity characterization by varying the process parameters of new underlap Silicon-on-Insulator (SOI) MOSFETs (with high-k stack on spacer) in single gate (SG) and double gate (DG) configurations. Using linearity defined in-terms of third order intercept (IP3), the paper presents guideline for optimum value of spacer “s”, film thickness $“T_{si}”and$ doping gradient “d” to maximize the linearity of new underlap design. Based on a new Figure-of-Merit (FoM) involving intrinsic gain $A_{v},$ IP3, maximum oscillation frequency $f_{MAX}$ and dc power consumption $P_{DC},$ it has been found that FoM in DG configuration is almost three times higher than that of SG design. This is due to a combination of higher value of $f_{MAX},$ $A_{v}$ and IP3 in DG configuration with power consumption of ~ 2.1 mW. The higher value of FoM in DG device has been achieved at similar “on” to “off” current ratio $(I_{on}/I_{off})$ as specified in current International Technology Road map for Semiconductors (ITRS). |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 1255901 |
| Page Count | 5 |
| File Format | |
| e-ISBN | 9781479922758 |
| DOI | 10.1109/INDCON.2013.6726009 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-12-13 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Performance evaluation Radio frequency MOSFET Films Silicon-on-Insulator Linearity Non-Linearity Low Power Doping Logic gates Underlap design Double Gate |
| Content Type | Text |
| Resource Type | Article |
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