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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gupta, K. Pandey, N. Gupta, M. |
| Copyright Year | 2010 |
| Description | Author affiliation: Electronics and Communication Division, Delhi Technological University, New Delhi, India (Gupta, K.; Pandey, N.) || Electronics and Communi cation Division, Netaji Subhash Institute of Technology, Delhi University, New Delhi, India (Gupta, M.) |
| Abstract | This paper proposes a new active shunt-peaked realization for MOS Current Mode Logic (MCML) based memory element. The circuit proposes the use of active inductors in shunt-peaking of MCML memory element. The technique of shunt-peaking offers a way of enhancing the performance of gates at high speed of operations. The benefit of the proposed circuit is verified by designing and simulating various MCML based memory elements with resistive, PMOS, feedback and active inductor load. An overall performance evaluation in terms of setup time, hold time and propagation delay from clock-to-Q has been done in PSPICE using 0.18μm TSMC CMOS technology parameters. For a power supply of 3.3 V and clock frequency of 1 GHz, the simulation results show an improvement of 13 to 25 percent in the values of delay parameters for active shunt-peaked memory element in comparison to other existing MCML based designs. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 179108 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424490721 |
| e-ISBN | 9781424490745 |
| DOI | 10.1109/INDCON.2010.5712660 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-12-17 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Active inductors Current mode logic shunt-peaking Logic gates CMOS integrated circuits Transistors Integrated circuit modeling Delay Load modeling memory element |
| Content Type | Text |
| Resource Type | Article |
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