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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xingsheng Wang Binjie Cheng Roy, S. Asenov, A. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow (Xingsheng Wang; Binjie Cheng; Roy, S.; Asenov, A.) |
| Abstract | We present a 3D simulation methodology aiming to capture the impact of strain on the line edge roughness (LER) induced variability in nMOSFETs. It includes both process and device simulation calibrated in respect of real 35 nm gate length nMOSFETs. Statistical LER of the gate pattern is introduced at the process simulation stage, and the impact of strain on the LER induced variability is investigated in Silicon nMOSFETs for the first time. Gate LER introduces both doping profile variability, and variability in the strain distribution in the channel, both contributing to the statistical variability in device electrical characteristics. |
| Starting Page | 89 |
| Ending Page | 92 |
| File Size | 506435 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424417292 |
| DOI | 10.1109/ULIS.2008.4527147 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-03-12 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Fluctuations Computational modeling Doping profiles Capacitive sensors strain variability MOSFETs Tensile strain Implants strained silicon intrinsic parameter fluctuations Silicon Power system reliability line edge roughness Thermal stresses |
| Content Type | Text |
| Resource Type | Article |
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